Improvements in the size, formation, density, and packaging of integrated circuits (“ICs”) have led the semiconductor industry to experience rapid growth. Improvements in integration density have led to decreased IC feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (“2D”) in nature, in that the volume occupied by the integrated components is essentially on the surface of a semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D IC formations, there are physical limits to density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Another is the increased design complexity for increased density 2D IC formations.
One attempt to increase circuit density is to stack two IC dies on top of each other to form what is referred to as a three-dimensional (“3D”) IC. In a typical 3D IC formation process, two dies are bonded together and electrical connections are formed between each die and contact pads on a substrate. For example, two dies may be bonded on top of each other with the lower die being coupled to a substrate.
Another 3D package which increases circuit density is referred to as a “Package-on-Package” (“PoP”) structure, wherein multiple dies coupled to respective substrates (e.g., an interposer) can be “stacked” on top of each other and coupled together. To form a PoP structure, a first die is electrically coupled to a first substrate to form a first circuit. The first circuit includes first connection points for connecting to a second circuit. The second circuit includes a second die and substrate having connection points on each side of the substrate. The first circuit is stacked and electrically coupled on top of the second circuit to form the PoP structure. The PoP structure can then be electrically coupled to a printed circuit board (“PCB”) or the like.
In this manner, PoP structures provide increased feature density for ICs which enables more functionality to be integrated into an IC package within a minimized surface area or “footprint” on a PCB.